This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-175041, filed Jun. 11, 2001; No. 2001-276801, filed Sep. 12, 2001; No. 2001-298311, filed Sep. 27, 2001, the entire contents of all of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a RESURF (REduced SURface Field) layer and, more particularly, to a technology applied to a high-power semiconductor device.
2. Description of the Related Art
Conventionally, vertical power MOS transistors are widely known. The ON resistance of a vertical power MOS transistor greatly depends on the electrical resistance of a conducting layer (drift layer) portion. The electrical resistance of a drift layer is determined by the impurity concentration in the drift layer. The impurity concentration in the drift layer also serves as a factor that determines the breakdown voltage of p-n junction formed by junction between a base layer and the drift layer. That is, the breakdown voltage and ON resistance have a tradeoff relationship. Hence, to improve the breakdown voltage and reduce the ON resistance at the same time, the tradeoff relationship must be improved.
As a technology for improving the tradeoff relationship, a structure in which a RESURF layer is buried in a drift layer is known. This structure is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-183348. A conventional power MOS transistor having this structure will be described with reference to FIG. 1. FIG. 1 is a sectional view of a vertical power MOS transistor.
As shown in FIG. 1, an nxe2x88x92-type drift layer 110 is formed on an n+-type drain layer 100. In the surface region of the drift layer 110, a plurality of p-type base layers 120 are periodically arranged in a direction perpendicular to the direction of depth. N+-type source layers 130 are selectively formed in the surface region of each base layer 120. A gate electrode 150 is formed on the base layers 120 and drift layer 110 between adjacent source layers 130 with a gate insulating film 140 interposed therebetween. A drain electrode 160 and source electrodes 170 are formed on the lower surface of the drain layer 100 and the source layers 130, respectively. Pillar-shaped p-type RESURF layers 180 are periodically formed in the drift layer 110.
With the above structure, since the RESURF layers 180 are formed deep in the drift layer 110, the drift layer 110 is readily fully depleted. Once the drift layer 110 is depleted, carriers in the drift layer 110 are not concerned in the breakdown voltage anymore. Hence, the impurity concentration in the drift layer 110 can be increased, and the ON resistance can be reduced. When the width of the drift layer 110, i.e., the periodical width between the RESURF layers 180 is decreased, the drift layer 110 is quickly fully depleted. When the depth of the RESURF layers 180 is increased, the breakdown voltage increases. Especially, to obtain the above effects, it is important to almost equalize the impurity concentration in the RESURF layers 180 with that in the drift layer 110.
A power MOS transistor is sometimes used to arrange a switching power supply or inverter. In this case, instead of connecting a high-speed diode in parallel to the current path of the MOS transistor, an internal diode formed by the drift layer 110 and base layer 120 may be operated. Hence, in a MOS transistor, not only the ON characteristic and switching characteristic but also the recovery characteristic of the internal diode is also important. Particularly, a reverse recovery characteristic when an internal diode shifts from an ON state to an OFF state is important. Even in a MOS transistor having no RESURF layers 180, the reverse recovery characteristic of the internal diode is different from that of a normal high-speed diode in, e.g., the reverse recovery current or reverse recovery time. Basically, however, the current waveform in reverse recovery is smooth, so a soft recovery waveform can be obtained. To the contrary, in a MOS transistor having the RESURF layers 180, the current flowing to the internal diode in reverse recovery abruptly changes. Hence, only a hard recovery waveform can be obtained. This may result in noise.
The two kinds of MOS transistors have different recovery characteristics because the drift layer 110 is depleted in different manners. In a normal MOS transistor, the drift layer 110 is gradually depleted as the applied voltage rises. However, in a MOS transistor having the RESURF layers 180, the drift layer 110 is completely depleted by a low applied voltage. That is, carriers in the drift layer 110 quickly disappear. For this reason, in reverse recovery of the internal diode, the current abruptly changes to 0, i.e., a hard recovery waveform is obtained.
Main manufacturing methods of a power MOS transistor with the above structure are as follows.
(1) Trenches are formed in the drift layer 110 and filled with the RESURF layers 180 by crystal growth.
(2) Crystal growth of the drift layer 110 and ion implantation to form the RESURF layers 180 in the drift layer 110 are repeated.
In the method (1), in forming the RESURF layers 180, crystal growth progresses at the corner portions of a trench bottom portion from both the bottom portion and the side surfaces. For this reason, the crystallinity of the RESURF layer 180 deteriorates at the corner portions of the trench bottom portion. This may make the breakdown voltage low. In addition, since the crystal growth rate in the upper portion differs from that in the lower portion of a trench, a cavity may be generated in the trench. In this case, the thickness of the RESURF layer 180 with a cavity may be different from that of the RESURF layer 180 without any cavity. This may lower the breakdown voltage.
In the method (2), each RESURF layer 180 is formed as p-type impurity ions implanted for every crystal growth are diffused into the drift layer 110 and connected to each other. Hence, a plurality of crystal growth interfaces are present in the drift layer 110 and RESURF layer 180. Due to disorder in crystallinity or mixing of an unexpected impurity, the breakdown voltage may become low, or the electrical characteristic may degrade. If the growth thickness for every crystal growth is increased, the p-type impurity must be diffused in a wide range. Since the impurity is also diffused in the horizontal direction, the unit cell width of the semiconductor element increases. That is, to form a thin and deep RESURF layer 180 to reduce the cell width, the crystal growth process and ion implantation process must be repeated many times. This makes the process very complex and also increases the number of growth interfaces.
In either the method (1) or (2), it is difficult to cause all the RESURF layer 180 to have the same depth. As described above, the depth of the RESURF layer 180 is an important factor of the breakdown voltage. Hence, if the RESURF layers 180 have different depths, the breakdown voltage varies.
A semiconductor device according to an aspect of the present invention comprises:
a drain layer having a first conductivity type;
a first drift layer having the first conductivity type and formed on the drain layer;
second drift layers having the first conductivity type and RESURF layers having a second conductivity type, which are formed on the first drift layer and periodically arranged in a direction perpendicular to a direction of depth, the RESURF layer forming a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer, and the first drift layer having an impurity concentration different from that in the second drift layer;
a drain electrode electrically connected to the drain layer;
a base layer having the second conductivity type and selectively formed in surface regions of the second drift layer and RESURF layer;
a source layer having the first conductivity type and selectively formed in a surface region of the base layer;
a source electrode formed in contact with surfaces of the base layer and source layer; and
a gate electrode formed on the base layer located between the source layer and the second drift layer with a gate insulating film interposed therebetween.
A method for fabricating a semiconductor device according to an aspect of the present invention comprises:
forming a first drift layer having a first conductivity type on a drain layer having the first conductivity type;
forming a trench in a surface region of the first drift layer;
forming a first RESURF layer having a second conductivity type by doping an impurity into an inner wall side surface of the trench;
forming a second drift layer having the first conductivity type in the trench;
selectively forming a base layer having the second conductivity type in surface regions of the first and second drift layers and first RESURF layer;
selectively forming a source layer having the first conductivity type in a surface region of the base layer;
forming a gate insulating film on the base layer located at least between the first drift layer and the source layer and between the second drift layer and the source layer; and
forming a gate electrode on the gate insulating film.